diff --git a/include/pci.h b/include/pci.h
index 739d863..86ee820 100755
--- a/include/pci.h
+++ b/include/pci.h
@@ -2,16 +2,43 @@
 /* COS2000 - Compatible Operating System - LGPL v3 - Hordé Nicolas             */
 /*                                                                             */
 
-typedef struct pcidev {
+
+
+typedef struct pciclass {
+	u16 number;
+	u8 *name;
+} pciclass  __attribute__ ((packed));	
+
+typedef struct pcidev
+{
+    u16 vendor_id;
+    u16 device_id;
+    u16 command;
+    u16 status;
+    u8 revision_id;
+    u8 interface;
+    u8 sub_class;
+    u8 base_class;
+    u8 cache_line_size;
+    u8 latency_timer;
+    u8 header_type;
+    u8 bist;
+} pcidev  __attribute__ ((packed));	
+
+
+typedef struct pcidevmini {
   union {
     struct {
-        u16 vendor;
-        u16 device;
+        u16 vendor_id;
+        u16 device_id;
     };
    u32 dword;
   };
-} pcidev  __attribute__ ((packed));	
+} pcidevmini  __attribute__ ((packed));	
 
 u16 pciConfigReadWord(const u8 bus, const u8 dev, const u8 function, const u8 offset);
+void scanPCImini(void);
+pcidevmini getPCImininfo(const u8 bus, const u8 dev, const u8 function);
+bool getPCInfo(pcidev *device, const u8 bus, const u8 dev, const u8 function);
 void scanPCI(void);
-pcidev getPCImininfo(const u8 bus, const u8 dev, const u8 function);
+u8 * pcigetclassname( const pcidev *device);
diff --git a/lib/PCI/class.c b/lib/PCI/class.c
new file mode 100644
index 0000000..73a04e7
--- /dev/null
+++ b/lib/PCI/class.c
@@ -0,0 +1,194 @@
+static pciclass old[] = {
+	{ 0x0, "Pre-2.0 PCI Specification Device, Non-VGA" },
+	{ 0x1, "Pre-2.0 PCI Specification Device, VGA Compatible" },
+	{ 0, NULL }
+};
+
+static pciclass storage[] = {
+	{ 0x00, "Mass Storage Controller, SCSI" },
+	{ 0x01, "Mass Storage Controller, IDE" },
+	{ 0x02, "Mass Storage Controller, Floppy" },
+	{ 0x03, "Mass Storage Controller, IPI" },
+	{ 0x04, "Mass Storage Controller, RAID" },
+	{ 0x05, "Mass Storage Controller, ATA controller with single DMA" }, 
+	{ 0x06, "Mass Storage Controller, SATA" },
+	{ 0x07, "Mass Storage Controller, SAS" },
+	{ 0x08, "Mass Storage Controller, NVM" },
+	{ 0x80, "Mass Storage Controller, Other" },
+	{ 0, NULL }
+};
+
+static pciclass network[] = {
+	{ 0x00, "Network Controller, Ethernet" },
+	{ 0x01, "Network Controller, Token Ring" },
+	{ 0x02, "Network Controller, FDDI" },
+	{ 0x03, "Network Controller, ATM" },
+	{ 0x04, "Network Controller, ISDN" },
+	{ 0x80, "Network Controller, Other" },
+	{ 0, NULL }
+};
+
+static pciclass display[] = {
+	{ 0x00, "Display Controller, VGA" },
+	{ 0x01, "Display Controller, XGA" },
+	{ 0x02, "Display Controller, 3D" },
+	{ 0x80, "Display Controller, Other" },
+	{ 0, NULL }
+};
+
+static pciclass multimedia[] = {
+	{ 0x00, "Multimedia Device, Video" },
+	{ 0x01, "Multimedia Device, Audio" },
+	{ 0x02, "Multimedia Device, Telephony" },
+	{ 0x03, "Multimedia Device, HDA" },
+	{ 0x80, "Multimedia Device, Other" },
+	{ 0, NULL }
+};
+
+static pciclass memory[] = {
+	{ 0x00, "Memory Controller, RAM" },
+	{ 0x01, "Memory Controller, Flash" },
+	{ 0x80, "Memory Controller, Other" },
+	{ 0, NULL }
+};
+
+static pciclass bridge[] = {
+	{ 0x00, "Bridge Device, Host/PCI" },
+	{ 0x01, "Bridge Device, PCI/ISA" },
+	{ 0x02, "Bridge Device, PCI/EISA" },
+	{ 0x03, "Bridge Device, PCI/Micro Channel" },
+	{ 0x04, "Bridge Device, PCI/PCI" },
+	{ 0x05, "Bridge Device, PCI/PCMCIA" },
+	{ 0x06, "Bridge Device, PCI/NuBus" },
+	{ 0x07, "Bridge Device, PCI/CardBus" },
+	{ 0x08, "Bridge Device, PCI/RACEway" },
+	{ 0x09, "Bridge Device, PCI/Transparent" },
+	{ 0x0a, "Bridge Device, Infiniband" },
+	{ 0x80, "Bridge Device, Other" },
+	{ 0, NULL }
+};
+
+static pciclass simplecomm[] = {
+	{ 0x00, "Simple Communications Controller, Serial" },
+	{ 0x01, "Simple Communications Controller, Parallel" },
+	{ 0x02, "Simple Communications Controller, Multiport" },
+	{ 0x03, "Simple Communications Controller, Modem" },
+	{ 0x04, "Simple Communications Controller, GPIB" },
+	{ 0x05, "Simple Communications Controller, Smart Card" },
+	{ 0x80, "Simple Communications Controller, Other" },
+	{ 0, NULL }
+};
+
+static pciclass baseperiph[] = {
+	{ 0x00, "Base Systems Peripheral, Interrupt Controller" },
+	{ 0x01, "Base Systems Peripheral, DMA" },
+	{ 0x02, "Base Systems Peripheral, System Timer" },
+	{ 0x03, "Base Systems Peripheral, Real Time Clock" },
+	{ 0x04, "Base Systems Peripheral, PCI Hot-plug" },
+	{ 0x05, "Base Systems Peripheral, SD Host Controller" },
+	{ 0x06, "Base Systems Peripheral, IOMMU" },
+	{ 0x80, "Base Systems Peripheral, Other" },
+	{ 0, NULL }
+};
+
+static pciclass input[] = {
+	{ 0x00, "Input Device, Keyboard" },
+	{ 0x01, "Input Device, Digitizer" },
+	{ 0x02, "Input Device, Mouse" },
+	{ 0x03, "Input Device, Scanner" },
+	{ 0x04, "Input Device, Game Port" },
+	{ 0x80, "Input Device, Other" },
+	{ 0, NULL }
+};
+
+static pciclass docking[] = {
+	{ 0x00, "Docking Station, Generic" },
+	{ 0x80, "Docking Station, Other" },
+	{ 0, NULL }
+};
+
+static pciclass processor[] = {
+	{ 0x00, "Processor, i386" },
+	{ 0x01, "Processor, i486" },
+	{ 0x02, "Processor, Pentium" },
+	{ 0x10, "Processor, Alpha" },
+	{ 0x20, "Processor, Power PC" },
+	{ 0x80, "Processor, Co-processor" },
+	{ 0, NULL }
+};
+
+static pciclass serial[] = {
+	{ 0x00, "Serial Bus Controller, Firewire" },
+	{ 0x01, "Serial Bus Controller, ACCESS.bus" },
+	{ 0x02, "Serial Bus Controller, SSA" },
+	{ 0x03, "Serial Bus Controller, USB" },
+	{ 0x04, "Serial Bus Controller, Fibre Channel" },
+	{ 0x05, "Serial Bus Controller, SMBus" },
+	{ 0x06, "Serial Bus Controller, Inifiniband" },
+	{ 0x07, "Serial Bus Controller, IPMI" },
+	{ 0, NULL }
+};
+
+static pciclass wireless[] = {
+	{ 0x00, "Wireless Controller, iRDA" },
+	{ 0x01, "Wireless Controller, IR" },
+	{ 0x10, "Wireless Controller, RF" },
+	{ 0x11, "Wireless Controller, Bluetooth" },
+	{ 0x12, "Wireless Controller, Broadband" },
+	{ 0x20, "Wireless Controller, 802.11a" },
+	{ 0x21, "Wireless Controller, 802.11b" },
+	{ 0x80, "Wireless Controller, Other" },
+	{ 0, NULL }
+};
+
+static pciclass intelliio[] = {
+	{ 0x00, "Intelligent IO Controller, I2O" },
+	{ 0, NULL }
+};
+
+static pciclass satcomm[] = {
+	{ 0x00, "Satellite Communication Controller, TV" },
+	{ 0x01, "Satellite Communication Controller, Audio" },
+	{ 0x02, "Satellite Communication Controller, Voice" },
+	{ 0x03, "Satellite Communication Controller, Data" },
+	{ 0, NULL }
+};
+
+static pciclass crypto[] = {
+	{ 0x00, "Encryption/Decryption Controller, Network/computer" },
+	{ 0x01, "Encryption/Decryption Controller, Entertainment" },
+	{ 0x80, "Encryption/Decryption Controller, Other" },
+	{ 0, NULL }
+};
+
+static pciclass dasp[] = {
+	{ 0x00, "Data Acquisition and Signal Processing Controller, DPIO" },
+	{ 0x01, "Data Acquisition and Signal Processing Controller, Performance Counter" },
+	{ 0x10, "Data Acquisition and Signal Processing Controller, Communications Synchronization" },
+	{ 0x20, "Data Acquisition and Signal Processing Controller, Management Card" },
+	{ 0x80, "Data Acquisition and Signal Processing Controller, Other" },
+	{ 0, NULL }
+};
+
+static pciclass *classcodes[] = {
+	old,
+	storage,
+	network,
+	display,
+	multimedia,
+	memory,
+	bridge,
+	simplecomm,
+	baseperiph,
+	input,
+	docking,
+	processor,
+	serial,
+	wireless,
+	intelliio,
+	satcomm,
+	crypto,
+	dasp,
+	[255] = NULL
+};
+
diff --git a/lib/pci.c b/lib/pci.c
index 0c6bc19..d291b75 100755
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -5,23 +5,79 @@
 #include "asm.h"
 #include "types.h"
 #include "pci.h"
+#include "PCI/class.c"
 
 #define MAX_BUS_SCAN        256
 #define MAX_DEVICE_SCAN     32
 #define MAX_FUNCTION_SCAN   8
 
+/*******************************************************************************/
+/* Retourne une chaine correspondant à l'ID class/subclass PCI */
+
+u8 * pcigetclassname( const pcidev *device)
+{
+    pciclass *class = NULL;
+	if ( device == NULL ) {
+		return NULL;
+	}
+	if ( device->base_class == 0xff ) {
+		return "Unassigned class";
+	}
+	class = classcodes[device->base_class];
+	if (!class) {
+		return "Unknowned class";
+	}
+	while (class->name != NULL) {
+		if (class->number == device->sub_class) {
+			return class->name;
+		}
+		class++;
+	}
+
+	return "Unknowned class";
+}
+
 /*******************************************************************************/
 /* Récupère les identifiants vendeur / periphérique du periphérique PCI donnée */
 
-pcidev getPCImininfo(const u8 bus, const u8 dev, const u8 function)
+pcidevmini getPCImininfo(const u8 bus, const u8 dev, const u8 function)
 {
-    pcidev result;
-    if ((result.vendor = pciConfigReadWord(bus,dev,function,0x0)) != 0xFFFF) {
-       result.device = pciConfigReadWord(bus,dev,function,0x2);
+    pcidevmini result;
+    if ((result.vendor_id = pciConfigReadWord(bus,dev,function,0x0)) != 0xFFFF) {
+       result.device_id = pciConfigReadWord(bus,dev,function,0x2);
     }
     return result;
 }
 
+/*******************************************************************************/
+/* Récupère toutes les informations du periphérique PCI donnée */
+
+bool getPCInfo(pcidev *device, const u8 bus, const u8 dev, const u8 function)
+{
+    if ((device->vendor_id = pciConfigReadWord(bus,dev,function,0x0)) != 0xFFFF) 
+    {
+        u16 temp;
+        device->device_id = pciConfigReadWord(bus,dev,function,0x2);
+        device->command = pciConfigReadWord(bus,dev,function,0x4);
+        device->status = pciConfigReadWord(bus,dev,function,0x6);
+        temp=pciConfigReadWord(bus,dev,function,0x8);
+        device->revision_id = temp & 0xFF;
+        device->interface = temp>>8;
+        temp=pciConfigReadWord(bus,dev,function,0xA);
+        device->sub_class = temp & 0xFF;
+        device->base_class = temp>>8;
+        temp=pciConfigReadWord(bus,dev,function,0xC);
+        device->cache_line_size = temp & 0xFF;
+        device->latency_timer = temp>>8;
+        temp=pciConfigReadWord(bus,dev,function,0xE);
+        device->header_type = temp & 0xFF;
+        device->bist = temp>>8;
+        return true;
+    }
+    else
+        return false;
+}
+
 /*******************************************************************************/
 /* Récupère les informations sur le periphérique PCI donnée */
 
@@ -37,6 +93,25 @@ u16 pciConfigReadWord(const u8 bus, const u8 dev, const u8 function, const u8 of
 /*******************************************************************************/
 /* Scan le bus PCI et affiche les périphériques */
 
+void scanPCImini(void)
+{
+    u16 bus,device,function;
+    pcidevmini result;    
+    for (bus=0; bus<MAX_BUS_SCAN; ++bus)
+      for (device=0; device<MAX_DEVICE_SCAN; ++device)
+        for (function=0; function<MAX_FUNCTION_SCAN; ++function)
+        {
+          result = getPCImininfo(bus,device,function);
+          if (result.vendor_id != 0xFFFF)
+            printf("Bus:%hx Dev:%hx Func:%hx %hx:%hx\r\n",bus, device, function, result.vendor_id, result.device_id);
+        }
+    return;
+}
+
+/*******************************************************************************/
+
+/* Scan le bus PCI et affiche les périphériques */
+
 void scanPCI(void)
 {
     u16 bus,device,function;
@@ -44,11 +119,8 @@ void scanPCI(void)
     for (bus=0; bus<MAX_BUS_SCAN; ++bus)
       for (device=0; device<MAX_DEVICE_SCAN; ++device)
         for (function=0; function<MAX_FUNCTION_SCAN; ++function)
-        {
-          result = getPCImininfo(bus,device,function);
-          if (result.vendor != 0xFFFF)
-            printf("Bus:%hx Dev:%hx Func:%hx %hx:%hx\r\n",bus, device, function, result.vendor, result.device);
-        }
+          if (getPCInfo(&result,bus,device,function))
+            printf("Bus:%hx Dev:%hx Func:%hx %hx:%hx ->%s\r\n",bus, device, function, result.vendor_id, result.device_id,pcigetclassname(&result));
     return;
 }