869 lines
19 KiB
C
869 lines
19 KiB
C
/*******************************************************************************/
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/* COS2000 - Compatible Operating System - LGPL v3 - Hordé Nicolas */
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/* */
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#include "interrupts.h"
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#include "types.h"
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#include "asm.h"
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#include "memory.h"
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#include "video.h"
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#include "gdt.h"
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#include "system.h"
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#include "debug.h"
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#include "process.h"
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#define IDT_SIZE 256 /* nombre de descripteurs */
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/* registre idt */
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static struct idtr idtreg;
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/* table de IDT */
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static idtdes idt[IDT_SIZE];
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static u32 retry_address;
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/******************************************************************************/
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/* Initialise la reprise après erreur */
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void initretry(u32 address)
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{
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retry_address = address;
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}
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/******************************************************************************/
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/* Récupère l'adresse de reprise après erreur */
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u32 getinitretry(void)
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{
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return retry_address;
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}
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/******************************************************************************/
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/* Initialise le controleur d'interruption 8259A */
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void initpic(void)
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{
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/* MASTER */
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/* Initialisation de ICW1 */
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outb(PIC1_CMD, ICW1_INIT + ICW1_ICW4);
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nop();
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/* Initialisation de ICW2 - vecteur de depart = 32 */
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outb(PIC1_DATA, 0x20);
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nop();
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/* Initialisation de ICW3 */
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outb(PIC1_DATA, 0x04);
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nop();
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/* Initialisation de ICW4 */
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outb(PIC1_DATA, ICW4_8086);
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nop();
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/* masquage des interruptions */
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outb(PIC1_DATA, 0xFF);
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nop();
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/* SLAVE */
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/* Initialisation de ICW1 */
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outb(PIC2_CMD, ICW1_INIT + ICW1_ICW4);
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nop();
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/* Initialisation de ICW2 - vecteur de depart = 96 */
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outb(PIC2_DATA, 0x60);
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nop();
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/* Initialisation de ICW3 */
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outb(PIC2_DATA, 0x02);
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nop();
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/* Initialisation de ICW4 */
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outb(PIC2_DATA, ICW4_8086);
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nop();
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/* masquage des interruptions */
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outb(PIC2_DATA, 0xFF);
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nop();
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/* Demasquage des irqs sauf clavier
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outb(PIC1_DATA,0xFD);
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nop();
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*/
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}
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/******************************************************************************/
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/* Active une IRQ */
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void enableirq(u8 irq)
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{
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u16 port;
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cli();
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port = (((irq & 0x08) << 4) + PIC1_DATA);
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outb(port, inb(port) & ~(1 << (irq & 7)));
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sti();
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}
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/******************************************************************************/
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/* Désactive une IRQ */
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void disableirq(u8 irq)
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{
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u16 port;
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cli();
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port = (((irq & 0x08) << 4) + PIC1_DATA);
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outb(port, inb(port) | (1 << (irq & 7)));
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sti();
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}
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/******************************************************************************/
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/* Créé un descripteur pour l'IDT */
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void makeidtdes(u32 offset, u16 select, u16 type, idtdes * desc)
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{
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desc->offset0_15 = (offset & 0xffff);
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desc->select = select;
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desc->type = type;
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desc->offset16_31 = (offset & 0xffff0000) >> 16;
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return;
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}
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/******************************************************************************/
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/* Change une entrée dans l'IDT */
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void setidt(u32 offset, u16 select, u16 type, u16 index)
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{
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cli();
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idtdes *desc;
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desc = idtreg.base;
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desc[index].offset0_15 = (offset & 0xffff);
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desc[index].select = select;
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desc[index].type = type;
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desc[index].offset16_31 = (offset & 0xffff0000) >> 16;
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sti();
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}
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/******************************************************************************/
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/* Met une entrée dans l'IDT */
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void putidt(u32 offset, u16 select, u16 type, u16 index)
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{
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idtdes temp;
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makeidtdes(offset, select, type, &temp);
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idt[index] = temp;
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}
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/******************************************************************************/
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/* Affiche une erreur CPU et fige l'ordinateur */
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void cpuerror(const u8 * src, const regs * stack)
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{
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printf("\033[31m*** ERREUR CPU : %s *** \r\n", src);
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if (stack != NULL)
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show_cpu(stack);
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print("<Appuyer une touche pour continuer>\033[0m\r\n");
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sti();
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waitascii();
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initselectors(retry_address);
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/*while (true) {
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nop();
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} */
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}
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/******************************************************************************/
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/* Déclenché lors de l'appel d'une interruption */
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void interruption()
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{
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cli();
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pushad();
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print("Appel d'une interruption\r\n");
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popad();
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sti();
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iret();
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}
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/******************************************************************************/
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/* Les expections */
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void exception0()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#DE Divide error", dump);
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}
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void exception1()
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{
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cli();
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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changevc(6);
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clearscreen();
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show_lightcpu(dump);
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printf("\r\n\033[7m[P]\033[0m PAS A PAS \033[7m D \033[0m PAS A PAS DETAILLE \033[7m C \033[0m CONTINUER \033[7m S \033[0m STOPPER \033[7m V \033[0m VOIR \033[7m S \033[0m SCINDER");
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sti();
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u8 ascii = waitascii();
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cli();
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if (ascii == 'P' || ascii == 'p')
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setdebugreg(0,
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current->eip + disasm(current->eip, NULL,
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false), DBG_EXEC);
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else if (ascii == 'D' || ascii == 'd')
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setdebugreg(0, 0, DBG_CLEAR);
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else if (ascii == 'C' || ascii == 'c')
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setdebugreg(0, 0, DBG_CLEAR);
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else if (ascii == 'S' || ascii == 's')
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{
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changevc(0);
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sti();
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initselectors(retry_address);
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}
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changevc(0);
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restdebugcpu();
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iret();
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}
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void exception2()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("NMI Non-maskable hardware interrupt", dump);
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}
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void exception3()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#BP INT3 instruction", dump);
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}
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void exception4()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#OF INTO instruction detected overflow", dump);
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}
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void exception5()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#BR BOUND instruction detected overrange", dump);
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}
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void exception6()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#UD Invalid instruction opcode", dump);
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}
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void exception7()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#NM No coprocessor", dump);
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}
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void exception8()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#DF Double fault", dump);
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}
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void exception9()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("Coprocessor segment overrun", dump);
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}
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void exception10()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#TS Invalid task state segment (TSS)", dump);
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}
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void exception11()
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{
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regs *dump;
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exception_stack *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#NP Segment not present", dump);
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}
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void exception12()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#SS Stack fault", dump);
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}
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void exception13()
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{
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regs *dump;
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exception_stack *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#GP General protection fault (GPF)", dump);
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}
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static u8 ex14_errors1[] =
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"Supervisory process tried to read a non-present page entry";
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static u8 ex14_errors2[] =
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"Supervisory process tried to read a page and caused a protection fault";
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static u8 ex14_errors3[] =
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"Supervisory process tried to write to a non-present page entry";
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static u8 ex14_errors4[] =
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"Supervisory process tried to write a page and caused a protection fault";
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static u8 ex14_errors5[] =
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"User process tried to read a non-present page entry";
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static u8 ex14_errors6[] =
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"User process tried to read a page and caused a protection fault";
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static u8 ex14_errors7[] =
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"User process tried to write to a non-present page entry";
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static u8 ex14_errors8[] =
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"User process tried to write a page and caused a protection fault";
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static u8 *ex14_errors[] =
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{ &ex14_errors1, &ex14_errors2, &ex14_errors3, &ex14_errors4,
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&ex14_errors5, &ex14_errors6, &ex14_errors7, &ex14_errors8 };
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void exception14()
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{
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regs *dump;
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exception_stack *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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if (dump->cr2 >= USER_CODE && dump->cr2 < USER_STACK)
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{
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virtual_range_new(getcurrentprocess()->pdd,
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(u8 *) (dump->cr2 & 0xFFFFF000),
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PAGESIZE, PAGE_ALL);
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}
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else
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{
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printf("Page fault - %s at adress %Y cs:eip - %Y:%Y\r\n",
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ex14_errors[current->error_code & 0xF], dump->cr2,
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dump->cs, dump->eip);
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cpuerror("#PGF Page fault", dump);
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}
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restdebugcpu();
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iret();
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}
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void exception15()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("(reserved)", dump);
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}
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void exception16()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#MF Coprocessor error", dump);
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}
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void exception17()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#AC Alignment check", dump);
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}
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void exception18()
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{
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regs *dump;
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exception_stack_noerror *current;
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u32 *oldesp;
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getEBP(oldesp);
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dumpcpu();
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getESP(dump);
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current = (exception_stack *) (oldesp + 1);
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dump->ebp = *oldesp;
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dump->esp = (u32) oldesp + sizeof(exception_stack);
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dump->eip = current->eip;
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cpuerror("#MC Machine check", dump);
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}
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/******************************************************************************/
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/* Les IRQ par défaut */
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void irq0()
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{
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cli();
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pushf();
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pushad();
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print("irq 0");
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irqendmaster();
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popad();
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popf();
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sti();
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leave();
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iret();
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}
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void irq1()
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{
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cli();
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pushf();
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pushad();
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print("irq 1");
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while ((inb(0x64) & 1) == 0);
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inb(0x60);
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irqendmaster();
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popad();
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popf();
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sti();
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leave();
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iret();
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}
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void irq2()
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{
|
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cli();
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pushf();
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pushad();
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print("irq 2");
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irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq3()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 3");
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq4()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 4");
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq5()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 5");
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq6()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 6");
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq7()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 7");
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq8()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 8");
|
|
irqendslave();
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq9()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 9");
|
|
irqendslave();
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq10()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 10");
|
|
irqendslave();
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq11()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 11");
|
|
irqendslave();
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq12()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 12");
|
|
while ((inb(0x64) & 1) == 0);
|
|
inb(0x60);
|
|
irqendslave();
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq13()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 13");
|
|
irqendslave();
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq14()
|
|
{
|
|
cli();
|
|
pushf();
|
|
pushad();
|
|
print("irq 14");
|
|
irqendslave();
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
void irq15()
|
|
{
|
|
cli();
|
|
print("irq 15");
|
|
irqendslave();
|
|
irqendmaster();
|
|
popad();
|
|
popf();
|
|
sti();
|
|
leave();
|
|
iret();
|
|
}
|
|
|
|
/******************************************************************************/
|
|
/* Initialise une IDT */
|
|
|
|
void initidt(void)
|
|
{
|
|
u16 i;
|
|
putidt((u32) exception0, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 0);
|
|
putidt((u32) exception1, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 1);
|
|
putidt((u32) exception2, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 2);
|
|
putidt((u32) exception3, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 3);
|
|
putidt((u32) exception4, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 4);
|
|
putidt((u32) exception5, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 5);
|
|
putidt((u32) exception6, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 6);
|
|
putidt((u32) exception7, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 7);
|
|
putidt((u32) exception8, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 8);
|
|
putidt((u32) exception9, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 9);
|
|
putidt((u32) exception10, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 10);
|
|
putidt((u32) exception11, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 11);
|
|
putidt((u32) exception12, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 12);
|
|
putidt((u32) exception13, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 13);
|
|
putidt((u32) exception14, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 14);
|
|
putidt((u32) exception15, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 15);
|
|
putidt((u32) exception16, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 16);
|
|
putidt((u32) exception17, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 17);
|
|
putidt((u32) exception18, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 18);
|
|
for (i = 19; i < 32; i++)
|
|
{
|
|
putidt((u32) interruption, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING3 | TRAPGATE, i);
|
|
}
|
|
putidt((u32) irq0, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 32);
|
|
putidt((u32) irq1, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 33);
|
|
putidt((u32) irq2, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 34);
|
|
putidt((u32) irq3, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 35);
|
|
putidt((u32) irq4, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 36);
|
|
putidt((u32) irq5, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 37);
|
|
putidt((u32) irq6, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 38);
|
|
putidt((u32) irq7, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 39);
|
|
for (i = 40; i < 96; i++)
|
|
{
|
|
putidt((u32) interruption, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING3 | TRAPGATE, i);
|
|
}
|
|
putidt((u32) irq8, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 96);
|
|
putidt((u32) irq9, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 97);
|
|
putidt((u32) irq10, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 98);
|
|
putidt((u32) irq11, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 99);
|
|
putidt((u32) irq12, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 100);
|
|
putidt((u32) irq13, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 101);
|
|
putidt((u32) irq14, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 102);
|
|
putidt((u32) irq15, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | INTGATE, 103);
|
|
for (i = 104; i < IDT_SIZE; i++)
|
|
{
|
|
putidt((u32) interruption, SEL_KERNEL_CODE,
|
|
ENTRY_PRESENT | ENTRY_RING0 | TRAPGATE, i);
|
|
}
|
|
/* initialise le registre idt */
|
|
idtreg.limite = IDT_SIZE * sizeof(idtdes);
|
|
idtreg.base = IDT_ADDR;
|
|
/* recopie de la IDT a son adresse */
|
|
memcpy(&idt, (u8 *) idtreg.base, idtreg.limite, 1);
|
|
/* chargement du registre IDTR */
|
|
lidt(&idtreg);
|
|
}
|
|
|
|
/******************************************************************************/
|
|
/* 8253/8254 PIT (Programmable Interval Timer) Timer ajustable */
|
|
|
|
void inittimer(void)
|
|
{
|
|
u32 divisor = TIMER_FREQ / HZ;
|
|
outb(TIMER_MODE, RATE_GENERATOR);
|
|
outb(TIMER0, (u8) divisor);
|
|
outb(TIMER0, (u8) (divisor >> 8));
|
|
}
|
|
/*******************************************************************************/
|