564 lines
9.4 KiB
C
Executable File
564 lines
9.4 KiB
C
Executable File
#include "interrupts.h"
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#include "types.h"
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#include "asm.h"
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#include "memory.h"
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#include "video.h"
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#define SIZEIDT 256 /* nombre de descripteurs */
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#define BASEIDT 0x00000000 /* addr de la IDT */
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/* registre idt */
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static struct idtr idtreg;
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/* table de IDT */
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static idtdes idt[256];
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/******************************************************************************/
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/* Initialise le controleur d'interruption 8259A */
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void initpic(void)
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{
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/* MASTER */
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/* Initialisation de ICW1 */
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outb(PIC1_CMD, ICW1_INIT + ICW1_ICW4);
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nop();
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/* Initialisation de ICW2 - vecteur de depart = 32 */
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outb(PIC1_DATA, 0x20);
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nop();
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/* Initialisation de ICW3 */
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outb(PIC1_DATA, 0x04);
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nop();
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/* Initialisation de ICW4 */
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outb(PIC1_DATA, ICW4_8086);
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nop();
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/* masquage des interruptions */
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outb(PIC1_DATA, 0xFF);
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nop();
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/* SLAVE */
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/* Initialisation de ICW1 */
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outb(PIC2_CMD, ICW1_INIT + ICW1_ICW4);
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nop();
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/* Initialisation de ICW2 - vecteur de depart = 96 */
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outb(PIC2_DATA, 0x60);
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nop();
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/* Initialisation de ICW3 */
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outb(PIC2_DATA, 0x02);
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nop();
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/* Initialisation de ICW4 */
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outb(PIC2_DATA, ICW4_8086);
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nop();
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/* masquage des interruptions */
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outb(PIC2_DATA, 0xFF);
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nop();
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/* Demasquage des irqs sauf clavier
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outb(PIC1_DATA,0xFD);
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nop();
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*/
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}
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/******************************************************************************/
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/* Active une IRQ */
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void enableirq(u8 irq)
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{
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u16 port;
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cli();
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port = (((irq & 0x08) << 4) + PIC1_DATA);
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outb(port, inb(port) & ~(1 << (irq & 7)));
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sti();
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}
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/******************************************************************************/
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/* Désactive une IRQ */
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void disableirq(u8 irq)
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{
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u16 port;
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cli();
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port = (((irq & 0x08) << 4) + PIC1_DATA);
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outb(port, inb(port) | (1 << (irq & 7)));
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sti();
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}
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/******************************************************************************/
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/* Créé un descripteur pour l'IDT */
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void makeidtdes(u32 offset, u16 select, u16 type, idtdes * desc)
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{
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desc->offset0_15 = (offset & 0xffff);
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desc->select = select;
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desc->type = type;
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desc->offset16_31 = (offset & 0xffff0000) >> 16;
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return;
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}
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/******************************************************************************/
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/* Change une entrée dans l'IDT */
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void setidt(u32 offset, u16 select, u16 type, u16 index)
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{
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cli();
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idtdes *desc;
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desc = idtreg.base;
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desc[index].offset0_15 = (offset & 0xffff);
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desc[index].select = select;
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desc[index].type = type;
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desc[index].offset16_31 = (offset & 0xffff0000) >> 16;
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sti();
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}
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/******************************************************************************/
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/* Met une entrée dans l'IDT */
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void putidt(u32 offset, u16 select, u16 type, u16 index)
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{
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idtdes temp;
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makeidtdes(offset, select, type, &temp);
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idt[index] = temp;
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}
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/******************************************************************************/
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/* Affiche une erreur CPU et fige l'ordinateur */
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void cpuerror(const u8 * src)
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{
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print("\033[31m***** ERREUR CPU ****\r\n -");
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print(src);
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dump_regs();
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while (true) {
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nop();
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}
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}
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/******************************************************************************/
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/* Déclenché lors de l'appel d'une interruption */
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void interruption()
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{
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cli();
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pushf();
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pushad();
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print("Appel d'une interruption\r\n");
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popad();
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popf();
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sti();
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iret();
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}
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/******************************************************************************/
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/* Les expections */
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void exception0()
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{
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print("divide error\r\n");
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}
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void exception1()
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{
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cpuerror("debug exception\r\n");
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}
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void exception2()
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{
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cpuerror("non-maskable hardware interrupt\r\n");
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}
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void exception3()
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{
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cpuerror("INT3 instruction\r\n");
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}
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void exception4()
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{
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cpuerror("INTO instruction detected overflow\r\n");
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}
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void exception5()
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{
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print("BOUND instruction detected overrange\r\n");
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}
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void exception6()
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{
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cpuerror("invalid instruction opcode\r\n");
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}
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void exception7()
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{
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cpuerror("no coprocessor\r\n");
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}
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void exception8()
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{
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cpuerror("double fault\r\n");
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}
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void exception9()
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{
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cpuerror("coprocessor segment overrun\r\n");
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}
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void exception10()
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{
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cpuerror("invalid task state segment (TSS)\r\n");
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}
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void exception11()
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{
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cpuerror("segment not present\r\n");
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}
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void exception12()
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{
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cpuerror("stack fault");
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}
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void exception13()
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{
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cpuerror("general protection fault (GPF)\r\n");
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}
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void exception14()
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{
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cpuerror("page fault\r\n");
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}
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void exception15()
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{
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cpuerror("(reserved)\r\n");
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}
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void exception16()
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{
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cpuerror("coprocessor error\r\n");
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}
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void exception17()
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{
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cpuerror("alignment check\r\n");
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}
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void exception18()
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{
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cpuerror("machine check");
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}
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/******************************************************************************/
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/* Les IRQ par défaut */
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void irq0()
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{
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cli();
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pushf();
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pushad();
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print("irq 0");
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq1()
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{
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cli();
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pushf();
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pushad();
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print("irq 1");
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while ((inb(0x64) & 1) == 0) ;
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inb(0x60);
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x01C, %esp;");
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iret();
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}
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void irq2()
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{
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cli();
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pushf();
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pushad();
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print("irq 2");
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq3()
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{
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cli();
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pushf();
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pushad();
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print("irq 3");
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq4()
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{
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cli();
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pushf();
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pushad();
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print("irq 4");
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq5()
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{
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cli();
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pushf();
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pushad();
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print("irq 5");
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq6()
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{
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cli();
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pushf();
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pushad();
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print("irq 6");
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq7()
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{
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cli();
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pushf();
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pushad();
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print("irq 7");
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq8()
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{
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cli();
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pushf();
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pushad();
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print("irq 8");
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irqendslave();
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq9()
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{
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cli();
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pushf();
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pushad();
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print("irq 9");
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irqendslave();
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq10()
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{
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cli();
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pushf();
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pushad();
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print("irq 10");
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irqendslave();
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq11()
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{
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cli();
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pushf();
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pushad();
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print("irq 11");
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irqendslave();
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq12()
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{
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cli();
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pushf();
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pushad();
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print("irq 12");
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while ((inb(0x64) & 1) == 0) ;
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inb(0x60);
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irqendslave();
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x1C, %esp;");
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iret();
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}
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void irq13()
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{
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cli();
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pushf();
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pushad();
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print("irq 13");
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irqendslave();
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq14()
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{
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cli();
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pushf();
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pushad();
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print("irq 14");
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irqendslave();
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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void irq15()
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{
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cli();
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print("irq 15");
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irqendslave();
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irqendmaster();
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popad();
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popf();
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sti();
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asm("addl $0x0C, %esp;");
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iret();
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}
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/******************************************************************************/
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/* Initialise une IDT */
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void initidt(void)
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{
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u16 i;
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putidt((u32) exception0, 0x20, INTGATE, 0);
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putidt((u32) exception1, 0x20, INTGATE, 1);
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putidt((u32) exception2, 0x20, INTGATE, 2);
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putidt((u32) exception3, 0x20, INTGATE, 3);
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putidt((u32) exception4, 0x20, INTGATE, 4);
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putidt((u32) exception5, 0x20, INTGATE, 5);
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putidt((u32) exception6, 0x20, INTGATE, 6);
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putidt((u32) exception7, 0x20, INTGATE, 7);
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putidt((u32) exception8, 0x20, INTGATE, 8);
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putidt((u32) exception9, 0x20, INTGATE, 9);
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putidt((u32) exception10, 0x20, INTGATE, 10);
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putidt((u32) exception11, 0x20, INTGATE, 11);
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putidt((u32) exception12, 0x20, INTGATE, 12);
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putidt((u32) exception13, 0x20, INTGATE, 13);
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putidt((u32) exception14, 0x20, INTGATE, 14);
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putidt((u32) exception15, 0x20, INTGATE, 15);
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putidt((u32) exception16, 0x20, INTGATE, 16);
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putidt((u32) exception17, 0x20, INTGATE, 17);
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putidt((u32) exception18, 0x20, INTGATE, 18);
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for (i = 19; i < 32; i++) {
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putidt((u32) interruption, 0x20, TRAPGATE, i);
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}
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putidt((u32) irq0, 0x20, INTGATE, 32);
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putidt((u32) irq1, 0x20, INTGATE, 33);
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putidt((u32) irq2, 0x20, INTGATE, 34);
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putidt((u32) irq3, 0x20, INTGATE, 35);
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putidt((u32) irq4, 0x20, INTGATE, 36);
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putidt((u32) irq5, 0x20, INTGATE, 37);
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putidt((u32) irq6, 0x20, INTGATE, 38);
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putidt((u32) irq7, 0x20, INTGATE, 39);
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for (i = 40; i < 96; i++) {
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putidt((u32) interruption, 0x20, TRAPGATE, i);
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}
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putidt((u32) irq8, 0x20, INTGATE, 96);
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putidt((u32) irq9, 0x20, INTGATE, 97);
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putidt((u32) irq10, 0x20, INTGATE, 98);
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putidt((u32) irq11, 0x20, INTGATE, 99);
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putidt((u32) irq12, 0x20, INTGATE, 100);
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putidt((u32) irq13, 0x20, INTGATE, 101);
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putidt((u32) irq14, 0x20, INTGATE, 102);
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putidt((u32) irq15, 0x20, INTGATE, 103);
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for (i = 104; i < SIZEIDT; i++) {
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putidt((u32) interruption, 0x20, TRAPGATE, i);
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}
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/* initialise le registre idt */
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idtreg.limite = SIZEIDT * 8;
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idtreg.base = BASEIDT;
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/* recopie de la IDT a son adresse */
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memcpy(&idt, (u8 *) idtreg.base, idtreg.limite, 1);
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/* chargement du registre IDTR */
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lidt(&idtreg);
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}
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/******************************************************************************/
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/* 8253/8254 PIT (Programmable Interval Timer) Timer ajustable */
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void inittimer()
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{
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outb(TIMER_MODE, RATE_GENERATOR);
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outb(TIMER0, (u8) (TIMER_FREQ / HZ));
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outb(TIMER0, (u8) ((TIMER_FREQ / HZ) >> 8));
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}
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